Method for forming a memory structure using a modified surface topography and structure thereof

ABSTRACT

To increase the gate coupling ratio of a semiconductor device  10 , discrete elements  22 , such as nanocrystals, are deposited over a floating gate 16. In one embodiment, the discrete elements  22  are pre-formed in a vapor phase and are attached to the semiconductor device  10  by electrostatic force. In one embodiment, the discrete elements  22  are pre-formed in a different chamber than that where they are attached. In another embodiment, the same chamber is used for the entire deposition process. An optional, interfacial layer  17  may be formed between the floating gate  16  and the discrete elements  22.

FIELD OF THE INVENTION

This invention relates generally to semiconductor devices, and morespecifically, to memory devices.

BACKGROUND

In non-volatile memory devices it is desirable to increase the ratio ofa first capacitance, which is between a control gate and a floatinggate, to a second capacitance, which is between a floating gate and asubstrate. The ratio between the first and second capacitances is knownas the gate coupling ratio. By having a high gate coupling ratio smallerperipheries can be used, thus desirably saving chip space.

One way to increase the gate coupling ratio is to enlarge the width ofthe floating gates in a non-volatile memory. However, increasing thewidth of the floating gates undesirably increases the size of thenon-volatile memory device. In addition, as the width of the floatinggates increases spaces between floating gates decreases. The floatinggates are typically formed by depositing a conformal layer and thenetching the layer to form the floating gates. If the spaces between thefloating gates are too small, sub-lithographic processes are used toremove any unwanted portions of the layer to form the spaces.Sub-lithographic processes are expensive and difficult to control in amanufacturing environment. Therefore, a need exists for a manufacturableprocess to decrease the floating gates size without significantlydecreasing the gate coupling ratio.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example and is notlimited by the accompanying figures, in which like references indicatesimilar elements.

FIG. 1 illustrates a cross-sectional view of a semiconductor devicehaving tunnel dielectrics, floating gates, mask, and (isolation)trenches in accordance with an embodiment of the present invention;

FIG. 2 illustrates the semiconductor device of FIG. 1 after formingtrench fill material in the trenches in accordance with an embodiment ofthe present invention;

FIG. 3 illustrates the semiconductor device of FIG. 2 after formingdiscrete elements over the semiconductor device in accordance with anembodiment of the present invention;

FIG. 4 illustrates the semiconductor device of FIG. 2 after forming aninterface layer and discrete elements in accordance with anotherembodiment of the present invention;

FIG. 5 illustrates the semiconductor device of FIG. 3 after forming acontrol dielectric in accordance with an embodiment of the presentinvention; and

FIG. 6 illustrates the semiconductor device of FIG. 5 after forming acontrol gate in accordance with an embodiment of the present invention.

Skilled artisans appreciate that elements in the figures are illustratedfor simplicity and clarity and have not necessarily been drawn to scale.For example, the dimensions of some of the elements in the figures maybe exaggerated relative to other elements to help improve theunderstanding of the embodiments of the present invention.

DETAILED DESCRIPTION OF THE DRAWINGS

A semiconductor structure may be formed by providing a semiconductorsubstrate, forming a tunnel dielectric overlying the semiconductorsubstrate, forming a floating gate overlying the first tunneldielectric, forming a plurality of discrete elements over the firstfloating gate, forming a control dielectric overlying the plurality ofpre-formed discrete elements, and forming a control gate overlying thecontrol dielectric. In addition, an interfacial layer may optionally beformed overlying the floating gate, wherein the plurality of discreteelements are formed over the interfacial layer. In one embodiment, theplurality of discrete elements may be formed over the floating gate byproviding pre-formed discrete elements, and attaching the pre-formeddiscrete elements to a surface of the semiconductor substrate, overlyingthe interfacial layer, if present, and the floating gate. More detailsand alternative processes and resulting structures can be furtherunderstood with reference to the figures.

Shown in FIG. 1 is a portion of a semiconductor device 10 (e.g., anon-volatile memory device) having masks 18, floating gates 16, tunneldielectrics 14, and a semiconductor substrate 12 patterned to form(isolation) trenches 11. The semiconductor substrate 12 can be anysemiconductor material or combinations of materials, such as galliumarsenide, silicon germanium, silicon-on-insulator (SOI), silicon,monocrystalline silicon, the like, and combinations of the above. Thetunnel dielectrics 14, the floating gates 16, and the masks 18 areformed over the semiconductor substrate 12 prior to forming the trenches11. The tunnel dielectrics 14 may be silicon dioxide, trap-free siliconnitride, any other suitable insulating material, or combinations of theabove formed by thermal growth, thermally assisted diffusion ordeposition (e.g., chemical vapor deposition (CVD)), the like orcombinations of the above. In one embodiment, the tunnel dielectrics 14have thicknesses between approximately 5-15 nanometers. Formed over thetunnel dielectrics 14, the floating gates 16 may be polysilicon, a metal(e.g., titanium), any other conductive material (e.g., titaniumnitride), or combinations of the above. The floating gates 16 may beformed by any deposition process, such as CVD, and may be approximately50-200 nanometers thick.

After forming the floating gates 16, masks 18 are deposited over thesemiconductor device 10. The masks 18 may include one layer or more thanone layer. In one embodiment, the masks 18 may be a hardmask (e.g.,nitride) or a photoresist material. The masks 18 are patterned usingconventional processes known to a skilled artisan. In one embodiment,the masks 18 are used both to pattern the underlying floating gates 16and the tunnel dielectrics 14 and to etch the semiconductor substrate 12to form the trenches 11. In one embodiment, CF₄ is used to (dry) etchthe floating gates 16, the tunnel dielectrics 14, and the semiconductorsubstrate 12; however, other chemistries can be used. In anotherembodiment, a wet etch is performed. The sidewalls of the trenches 11are illustrated in FIG. 1 as being sloped which is an artifact of theetch process and will differ based on the process used. In oneembodiment, the width of the trenches 11 is approximately 100 to 300nanometers and the depth of the trenches 11 is approximately 200-500nanometers.

Since the floating gates 16, as shown in FIG. 1, are self aligned to thetrenches 11 the distance between the floating gates 16 is large enoughso that material between the floating gates 16 can be removed usinglithographic processes. In addition, the self alignment avoids otherproblems that may occur due to the overlapping of the floating gates andthe trench 11. Unfortunately, decreasing the width of the floating gates16 so that the floating gates 16 are self aligned to the trenches 11decreases the gate coupling ratio. However, as will be described below,the topography of the floating gates' 16 surfaces may be modified toincrease the gate coupling ratio by forming discrete elements. Thus, aswill become evident the decreased gate coupling ratio due to thefloating gate width is offset by the increased gate coupling due to themodification of the topography of the floating gates 16.

The modifications of the topography of the floating gates describedbelow can be used on any floating gate and achieve benefits. Thus, ifthe floating gate is not self-aligned and instead overlaps the trenchesthen the topographical modifications will increase the gate couplingratio.

After forming the trenches 11, a trench fill material 20 is formed overthe semiconductor device 10. In one embodiment, the trench fill material20 is deposited using CVD, however any other deposition process may beused, such as physical vapor deposition (PVD). The trench fill material20 may be silicon dioxide, any dielectric, or combinations of the above.In one embodiment, after depositing the trench fill material 20 thetrench fill material 20 is made coplanar with the top of the masks 18using chemical mechanical polishing (CMP), as illustrated in FIG. 2.

After planarizing the trench fill material 20 the masks 18 are removedusing conventional techniques. For example, if the masks 18 are anitride, a wet strip (e.g., phosphoric acid) may be used. Next, discreteelements 22 are formed over the floating gates 16. Discrete elements 22may be nanoclusters, nanocrystals, discrete storage elements, surfaceenhancing discrete elements, the like or combinations of the above. Thediscrete elements 22 may be a semiconductor material (e.g., silicon,germanium, the like or combinations of the above) or a conductivematerial (e.g., a metal or metal alloy). Thus, the discrete elements 22are substantially conductive.

The discrete elements 22 are formed spaced apart from each other. Inother words, the discrete elements 22 are physically isolated from eachother. In one embodiment, the discrete elements 22 are spaced apart atleast approximately 10 nanometers on average, or more specifically,approximately 20-40 nanometers on average. The discrete elements 22 maynot all be spaced equidistance from each other. For example, a firstdiscrete element 22 may be spaced apart from a second discrete element22 by approximately 11 nanometers and the second discrete element 22 maybe spaced apart from a third discrete element by approximately 9nanometers, but on average the first, second and third discrete elements22 are spaced apart at least approximately 10 nanometers.

As shown in FIGS. 3-6, two or more discrete elements 22 may combine witheach other to form one large discrete element 23, but all the discreteelements 22 are not in physical contact with each other. In oneembodiment, the discrete elements 22 have a diameter betweenapproximately 5 to 30 nanometers. While the discrete elements 22 mayvary in diameter, in one embodiment, the variation is no more than 10percent with respect to a mean diameter.

In one embodiment, the discrete elements 22 are the same material as thefloating gates 16 (e.g., silicon), which prevents the formation ofdiscrete elements 22. In other words, when the discrete elements 22nucleate on a layer made of the same material, the discrete elements 22will undesirably coalesce and form a continuous layer for energyreasons. Thus, to form the discrete elements 22 on the same materialthey are made of, the discrete elements nucleate before being in contactwith the surface of the floating gates 16. Thus, the discrete elements22 are pre-formed prior to contacting the floating gates 16. In oneembodiment, the discrete elements 22 nucleate in the gas/vapor phasefollowing pyrolysis (i.e., form gas phase nuclei) at high temperaturesof a silicon-containing precursor gas. In one embodiment, the precursorused is silane (SiH₄). The temperature used should be high enough todecompose the silane into silicon atoms and hydrogen gas in a gaseousphase. The silicon atoms then nucleate in the gas phase and grow byvapor deposition and coagulation. In one embodiment, the silicon nucleiare approximately 5 to 30 nanometers in diameter. In one embodiment, thetemperature used is greater than approximately 900 degrees Celsius andthe partial pressure of the silicon containing precursor is greater thanapproximately 0.1 torr. These temperatures are greater than those usedin typical low pressure chemical vapor deposition (LPCVD) processes forsilicon. After forming the nanocrystals they are attached to thesemiconductor device 10 by electrostatic forces; the nuclei are toosmall for gravity to be the attracting force. The formation, ionization,attachment stages of the depositions process may occur in the same ordifferent chambers or tools. Alternatively, the particles may bethermophoretically deposited on the wafer. Small particles present in atemperature gradient are driven from regions of higher temperature tocolder areas. For example, in low pressure environments, gas atomsimpinge on a nanoparticle at a higher rate on the hotter side because oftheir higher kinetic energy and thus drive it to colder areas. Thisthermophoretic motion may be exploited to deposit nanoparticles from ahot ambient onto the surface of a wafer held at a much lowertemperature.

In another embodiment, the discrete elements 22 are a different materialthan the floating gates 16. For example, the discrete elements 22 may bea metal and the floating gates 16 may be polysilicon or vice versa. Todeposit the discrete elements 22 in this embodiment, the nuclei can beformed in the vapor phase prior to attachment as discussed above, byLPCVD where the nuclei are formed on the surface of the floating gates16, or any other process, such as PVD or atomic layer deposition (ALD).Thus, the discrete elements 22 need not nucleate in a gas phase in thisembodiment.

In yet another embodiment, an interfacial layer 17 may be formed overthe floating gates 16, as shown in FIG. 4. In one embodiment, theinterfacial layer 17 is a dielectric, such as silicon dioxide. Inanother embodiment, the interfacial layer 17 may be conductive (e.g., ametal or metal alloy). The interfacial layer 17 is preferably a thinlayer (e.g., approximately 0.5 to 1 nm) so that it is electricallytransparent. If the interfacial layer 17 is thin enough it may coalesceinto balls during subsequent high temperature processing, which shouldnot affect the functionality of the semiconductor device 10. Theinterfacial layer 17 may be formed by CVD, PVD, ALD, diffusion, the likeor combinations of the above over the floating gate 16 and patternedusing the masks 18, as discussed above with regards to FIGS. 1 and 2.Alternatively, the interfacial layer 17 can be formed after removing themasks 18. In this embodiment, if the interfacial layer 17 is conductiveit may be patterned and removed using the masks (not shown) so that itdoes not electrically couple areas of the semiconductor device 10 thatare otherwise electrically isolated from each other by the trench fillmaterial 20. If the interfacial layer 17 is a dielectric it need not beremoved. The interfacial layer 17 may be present to form a layer that isa different material than that the discrete elements 22 and the floatinggates 16 so that deposition of nanocrystals via LPCVD can be used; thisis cheaper than depositing the discrete elements 22 where each nucleusis formed in the gas phase prior to its contact with the floating gate16. For example, if floating gates 16 and discrete elements 22 comprisesilicon, layer 17 can be silicon dioxide or silicon nitride.

In another embodiment, prefabricated discrete elements 22 may bedeposited on the semiconductor device 10 by wetting the semiconductordevice in a colloidal solution. The colloidal solution may include asolvent and pre-fabricated discrete elements. In one embodiment, awetting promoter is added to the colloidal solution to encourage uniformdistribution of the colloidal solution.

In the embodiments discussed above in regards to FIGS. 3 and 4, thediscrete elements 22 modify the topography of the floating gates 16 byincreasing the net surface area. Because the interfacial layer 17, ifpresent, is thin, the discrete materials 22 are not electricallyisolated from the floating gate if the interfacial layer 17 is adielectric. If the interfacial layer 17 is a metal the floating gatesare also not electrically isolated from the floating gates 16 andinstead, are coupled to the floating gates 16 via the interfacial layer17. By increasing the net surface area of the floating gates 16 the gatecoupling ratio is increased.

As illustrated in FIGS. 3-4, the discrete elements 22 are formed overthe floating gates 16 and the trenches 11 that are filled with trenchfill material 20. There is no need to remove the discrete elements 22over the trench fill material 20 since the discrete elements 22 do notcouple or short the floating gates 16 to each other. In other words,since the discrete elements 22 are physically isolated from each otherprocessing is simplified by eliminating a patterning process that wouldbe needed if the discrete elements 22 over the floating gates 16 werecoupled to each other. If a continuous layer, for example, was usedinstead of the discrete elements 22 a patterning process would be neededto remove portions of the continuous layer that are formed over thetrench fill material 20 so that the floating gates 16 did not shorttogether.

After forming the discrete elements 22, a control dielectric 24 isformed over the discrete elements 22, as shown in FIG. 5. Due to thespaces between the discrete elements 22, portions of the controldielectric 24 will be formed between the discrete elements 22. Thecontrol dielectric 24 will probably have a nonplanar topography due tothe presence of the underlying discrete elements 22. In one embodiment,the control dielectric 24 may be an insulating or dielectric layer orstack of layers. For example, the control dielectric 24 may be anoxide-nitride-oxide (ONO) stack (where, in one embodiment, the oxidesare silicon dioxide and the nitride is silicon nitride) or a high-k(high dielectric constant) material. As used herein, a high-k materialis a material with a dielectric constant greater than that of silicondioxide. The control dielectric 24 may be formed by deposition (e.g.,CVD, PVD, ALD, the like or combinations of the above), thermaloxidation, the like, or combinations of the above.

After forming the control dielectric 24, a control electrode (controlgate) 26 is formed over the semiconductor device 10. In one embodiment,the control electrode 26 is polysilicon, metal, any other conductivematerial, or combinations of the above. The control electrode 26 may beformed by CVD, PVD, ALD, the like or combinations of the above.Conventional processing as known to a skilled artisan can be performedafter forming the control electrode 24.

By now it should be appreciated that there has been provided amanufacturable process to decrease the floating gates size withoutsignificantly decreasing the gate coupling ratio. The spaces between thefloating gates are large enough to be removed using manufacturableprocesses and the altered topography of the floating gates will increasethe gate coupling ratio of the devices.

In the foregoing specification, the invention has been described withreference to specific embodiments. However, one of ordinary skill in theart appreciates that various modifications and changes can be madewithout departing from the scope of the present invention as set forthin the claims below. For example, the floating gates 16 need not be selfaligned to the trenches 11. Accordingly, the specification and figuresare to be regarded in an illustrative rather than a restrictive sense,and all such modifications are intended to be included within the scopeof the present invention.

Benefits, other advantages, and solutions to problems have beendescribed above with regard to specific embodiments. However, thebenefits, advantages, solutions to problems, and any element(s) that maycause any benefit, advantage, or solution to occur or become morepronounced are not to be construed as a critical, required, or essentialfeature or element of any or all the claims. As used herein, the terms“comprises,” “comprising,” or any other variation thereof, are intendedto cover a non-exclusive inclusion, such that a process, method,article, or apparatus that comprises a list of elements does not includeonly those elements but may include other elements not expressly listedor inherent to such process, method, article, or apparatus. The terms“a” or “an”, as used herein, are defined as one or more than one.Moreover, the terms “front”, “back”, “top”, “bottom”, “over”, “under”and the like in the description and in the claims, if any, are used fordescriptive purposes and not necessarily for describing permanentrelative positions. It is understood that the terms so used areinterchangeable under appropriate circumstances such that theembodiments of the invention described herein are, for example, capableof operation in other orientations than those illustrated or otherwisedescribed herein. The term “plurality”, as used herein, is defined astwo or more than two. The term “another”, as used herein, is defined asat least a second or more. The term “coupled”, as used herein, isdefined as connected, although not necessarily directly, and notnecessarily mechanically.

1. A method for forming a semiconductor structure, comprising: providinga semiconductor substrate; forming a first tunnel dielectric overlyingthe semiconductor substrate; forming a first floating gate overlying thefirst tunnel dielectric; depositing a plurality of pre-formed discreteelements over the first floating gate; forming a control dielectricoverlying the plurality of pre-formed discrete elements; and forming acontrol gate overlying the control dielectric.
 2. The method of claim 1,further comprising: forming an isolation trench in the semiconductorsubstrate; filling the isolation trench with a trench fill material;forming a second tunnel dielectric overlying the semiconductorsubstrate; and forming a second floating gate overlying the secondtunnel dielectric, wherein the trench fill material is between the firstfloating gate and the second floating gate.
 3. The method of claim 2,wherein depositing the plurality of pre-formed discrete elements overthe first floating gate further comprises depositing the plurality ofpre-formed discrete elements over the trench fill material and thesecond floating gate.
 4. The method of claim 3, wherein forming thecontrol dielectric is performed such that the control dielectricoverlies the plurality of pre-formed discrete elements overlying thefirst floating gate, the trench fill material, and the second floatinggate.
 5. The method of claim 1, wherein depositing the plurality ofpre-formed discrete elements over the first floating gate comprises:forming at least one of the plurality of pre-formed discrete elementsduring a gas phase nucleation, and after forming the at least one of theplurality of pre-formed discrete elements, attaching the at least one ofthe plurality of pre-formed discrete elements to a surface of thesemiconductor substrate over the first floating gate.
 6. The method ofclaim 5, wherein the gas phase nucleation is performed in a firstchamber and the attaching is performed in a second chamber.
 7. Themethod of claim 6, wherein the attaching is performed using forcesselected from the group consisting of electrostatic forces andthermophoretic forces.
 8. The method of claim 1, wherein the firstfloating gate comprises polysilicon.
 9. The method of claim 1, whereinthe first floating gate comprises metal.
 10. The method of claim 1,wherein forming the control dielectric comprises forming an oxide layeroverlying the plurality of pre-formed discrete elements and forming anitride layer overlying the oxide layer.
 11. The method of claim 1,wherein forming the control dielectric comprises forming a dielectriclayer having a high dielectric constant overlying the plurality ofpre-formed discrete elements.
 12. The method of claim 1, wherein theplurality of pre-formed discrete elements are further characterized aspre-fabricated discrete elements.
 13. The method of claim 1, wherein theplurality of pre-formed discrete elements comprise nanocrystals.
 14. Themethod of claim 1, wherein the plurality of pre-formed discrete elementscomprise discrete storage elements.
 15. The method of claim 1, whereineach of the plurality of pre-formed discrete elements comprise asubstantially conductive material.
 16. The method of claim 1, whereinafter depositing the plurality of pre-formed discrete elements, each ofthe plurality of pre-formed discrete elements is spaced apart from eachother by at least 10 nanometers on average.
 17. A method for forming asemiconductor structure, comprising: providing a semiconductorsubstrate; forming a first tunnel dielectric overlying the semiconductorsubstrate; forming a first floating gate overlying the first tunneldielectric; forming a first interfacial layer overlying the firstfloating gate; forming a plurality of discrete elements over the firstinterfacial layer; forming a control dielectric overlying the pluralityof discrete elements; and forming a control gate overlying the controldielectric.
 18. The method of claim 17, further comprising: forming anisolation trench in the semiconductor substrate; filling the isolationtrench with a trench fill material; forming a second tunnel dielectricoverlying the semiconductor substrate; forming a second floating gateoverlying the second tunnel dielectric; and forming a second interfaciallayer overlying the second floating gate, wherein the trench fillmaterial is between the first floating gate and the second floatinggate.
 19. The method of claim 18, wherein forming the plurality ofdiscrete elements over the first interfacial layer further comprisesdepositing the plurality of pre-formed discrete elements over the trenchfill material and the second interfacial layer.
 20. The method of claim19, wherein forming the control dielectric is performed such that thecontrol dielectric overlies the plurality of discrete elements overlyingthe first floating gate, the trench fill material, and the secondfloating gate.
 21. The method of claim 17, wherein the first floatinggate comprises one of polysilicon and metal.
 22. The method of claim 17,wherein the plurality of discrete elements comprise nanocrystals. 23.The method of claim 17, wherein the plurality of discrete elementscomprise discrete storage elements.
 24. The method of claim 17, whereineach of the plurality of discrete elements comprise a substantiallyconductive material.
 25. The method of claim 17, wherein forming theplurality of discrete elements over the first interfacial layer isperformed using a process selected from the group consisting of lowpressure chemical vapor deposition (LPCVD), physical vapor deposition(PVD), and atomic layer deposition (ALD).
 26. The method of claim 17,wherein after depositing the plurality of discrete elements, each of theplurality of discrete elements is spaced apart from each other by atleast 10 nanometers on average.
 27. The method of claim 17, whereinforming a first interfacial layer overlying the first floating gatecomprises forming an oxide layer overlying the first floating gate. 28.The method of claim 17, wherein forming a first interfacial layeroverlying the first floating gate comprises forming a metal layeroverlying the first floating gate.
 29. A semiconductor structure,comprising: a semiconductor substrate; a first tunnel dielectricoverlying the semiconductor substrate; a first floating gate overlyingthe first tunnel dielectric; a plurality of discrete elements over thefirst floating gate, wherein each of the plurality of discrete elementsare spaced apart from each other; a control dielectric overlying theplurality of discrete elements; and a control gate overlying the controldielectric.
 30. The semiconductor structure of claim 29, furthercomprising an interfacial layer overlying the first floating gate andunderlying the plurality of discrete elements.
 31. The semiconductorstructure of claim 29, further comprising: an isolation trench filledwith a trench fill material; a second tunnel dielectric overlying thesemiconductor substrate; and a second floating gate overlying the secondtunnel dielectric, wherein the trench fill material is between the firstfloating gate and the second floating gate.
 32. The semiconductorstructure of claim 31, wherein the plurality of discrete elementsoverlie the trench fill material and the second floating gate.
 33. Thesemiconductor structure of claim 29, wherein the first floating gatecomprises polysilicon.
 34. The semiconductor structure of claim 29,wherein the first floating gate comprises metal.
 35. The semiconductorstructure of claim 29, wherein the plurality of discrete elementscomprise nanocrystals.
 36. The semiconductor structure of claim 29,wherein the plurality of discrete elements comprise discrete storageelements.
 37. The semiconductor structure of claim 29, wherein each ofthe plurality of discrete elements comprise a substantially conductivematerial.
 38. The semiconductor structure of claim 29, wherein each ofthe plurality of discrete elements are spaced apart from each other byat least 10 nanometers.